general description the DS1086LPMB1 peripheral module provides the necessary hardware to interface the ds1086l 3.3v spread-spectrum econoscillator k to any system that utilizes pmod k -compatible expansion ports configurable for i 2 c communication. the ds1086l is a program - mable clock generator that produces a spread-spectrum (dithered) square-wave output of frequencies from 130khz to 66.6mhz. the selectable dithered output reduces radiated-emission peaks by dithering the frequency 0.5%, 1%, 2%, 4%, or 8% below the programmed frequency. the ds1086l has a power-down mode and an output-enable control for power-sensitive applications. refer to the ds1086l ic data sheet for detailed informa - tion regarding operation of the ic. features s user-programmable 130khz to 66.6mhz square wave s no external timing components required s 6-pin pmod-compatible connector (i 2 c) s example software written in c for portability s secondary header allows daisy-chaining of additional modules on the i 2 c bus s output header provides access to control signals for external circuitry s rohs compliant s proven pcb layout s fully assembled and tested _________________________________________________________________ maxim integrated products 1 19-6318; rev 0; 5/12 ordering information appears at end of data sheet. DS1086LPMB1 peripheral module econoscillator is a trademark of maxim integrated products, inc. pmod is a trademark of digilent inc. DS1086LPMB1 peripheral module for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com.
designation qty description j3 1 5-pin straight male header r1, r2, r8, r9, r10 5 4.7k i q 5% resistors (0603) r3, r4, r5 3 1k i q 5% resistors (0603) r6, r7 2 150k i q 5% resistors (0603) u1 1 3.3v spread-spectrum econoscillator (8 f sop) maxim ds1086lu+ 1 pcb: epcb1086l supplier phone website murata electronics north america, inc. 770-436-1300 www.murata-northamerica.com designation qty description c1 1 0.01 f f q 10%, 16v x7r ceramic capacitor (0603) murata grm188r71c103ka01d c2 1 0.1 f f q 10%, 16v x7r ceramic capacitor (0603) murata grm188r71c104ka01d j1 1 12-pin (2 x 6) right-angle male header j2 1 8-pin (2 x 4) straight male header pin signal description 1 pdn power-down. when the pin is high, the output buffer is enabled. when the pin is low, the master oscillator is disabled (power-down mode). 2 sprd dither enable. when the pin is high, the dither is enabled. when the pin is low, the dither is disabled. 3 scl i 2 c serial clock 4 sda i 2 c serial data 5 gnd ground 6 vcc power supply 7 oe output enable. when the pin is high, the output buffer is enabled. when the pin is low, the output is disabled but the master oscillator is still on. 8 n.c. not connected 9 scl i 2 c serial clock 10 sda i 2 c serial data 11 gnd ground 12 vcc power supply _________________________________________________________________ maxim integrated products 2 component supplier note: indicate that ou are using the pm hen contacting this component suppier. component list detailed description i 2 c interface the DS1086LPMB1 peripheral module can interface to the host in one of two ways. it can plug directly into a pmod-compatible port (configured for i 2 c) through con - nector j1, or in this case, other i 2 c boards can attach to the same i 2 c bus through connector j2. i 2 c interface (daisy-chaining modules) alternatively, the peripheral module can connect to other i 2 c-based pmod modules using a 4-conductor ribbon cable connecting to the j2 connector. in this situation, pins 1-4 and 5-8 of j2 provide two connections to the i 2 c bus, allowing the module to be inserted into an i 2 c bus daisy-chain. connector j1 provides connection of the module to the pmod host. the pin assignments and functions adhere to the pmod standard recommended by digilent. see table 1. the j2 connector allows the module to be connected through a daisy-chain from another i 2 c module and/or provide i 2 c and power connections to other i 2 c modules on the same bus. see table 2. table 1. connector j1 (i 2 c communication) DS1086LPMB1 peripheral module
pin signal description 1 scl i 2 c serial clock 2 sda i 2 c serial data 3 gnd ground 4 vcc power supply 5 scl i 2 c serial clock 6 sda i 2 c serial data 7 gnd ground 8 vcc power supply pin signal description 1 out oscillator output. the output frequency is set by the offset, dac, and prescaler registers. 2 gnd ground 3 sprd dither enable. when the pin is high, the dither is enabled. when the pin is low, the dither is disabled. 4 pdn power-down. when the pin is high, the output buffer is enabled. when the pin is low, the master oscillator is disabled (power-down mode). 5 oe output enable. when the pin is high, the output buffer is enabled. when the pin is low, the output is disabled but the master oscillator is still on. _________________________________________________________________ maxim integrated products 3 external control signals the ic implements pins to control output enable (oe), power-down (pdn), and dither enable (sprd). these pins can be controlled either by the host (through the pmod connector) or by external circuitry through the 5-pin output connector. in cases where one or more of these signals is driven from an external source, 1k i resistors r3, r4, and r5 limit the current to/from the host. however, this also increases the apparent load to the external driving source. if the external source is inca - pable of driving this load (1k i || 4.7k i ), the signal(s) from the host should either be put into three-state (open) or resistors r3, r4, and/or r5 should be removed. the j3 connector provides the output signal as well as external inputs to the control signals. note that the con - trol lines from the host (sprd, pnd , oe) must either be three-stated or the external control signals must be able to drive the additional load. see table 3. software and fpga code example software and drivers are available that execute directly without modification on several fpga devel - opment boards that support an integrated or synthe - sized microprocessor. these boards include the digilent nexys 3, avnet lx9, and avnet zedboard, although other platforms can be added over time. maxim provides complete xilinx ise projects containing hdl, platform studio, and sdk projects. in addition, a synthesized bit stream, ready for fpga download, is provided for the demonstration application. the software project (for the sdk) contains several source files intended to accelerate customer evalu - ation and design. these include a base application (maximmodules.c) that demonstrates module function - ality and uses an api interface (maximdevicespecific utilities.c) to set and access maxim device functions within a specific module. the source code is written in standard ansi c format, and all api documentation including theory/operation, register description, and function prototypes are documented in the api interface file (maximdevicespecificutilities.h & .c). the complete software kit is available for download www.maxim-ic.com. quick start instructions are also available as a separate document. table 2. connector j2 (i 2 c expansion) table 3. connector j3 (external interface) DS1086LPMB1 peripheral module
vc c gn d 4. 7k r2 vc c vc c 0. 01 uf c1 15 0 r6 gn d vc c 1k r3 oe pd n ou t 1 spr d 2 vc c 3 gn d 4 oe 5 pd n 6 sd a 7 scl 8 ds 10 86 l u1 0. 1uf c2 sprd gn d 1 2 3 4 5 6 7 8 j2 1 2 3 4 5 6 7 8 9 10 11 12 j1 oe pd n sp rd sc l a d s a d s scl gn d vc c gn d vc c 15 0 r7 1k r5 4. 7k r1 1k r4 vc c 4. 7k r8 vc c 4. 7k r1 0 vc c 4. 7k r9 ou t 1 2 3 4 5 j3 _________________________________________________________________ maxim integrated products 4 figure 1. DS1086LPMB11 peripheral module schematic DS1086LPMB1 peripheral module
_________________________________________________________________ maxim integrated products 5 figure 2. DS1086LPMB11 peripheral module component placement guidecomponent side figure 3. DS1086LPMB11 peripheral module pcb layoutcomponent side figure 4. DS1086LPMB11 peripheral module pcb layoutinner layer 1 (ground) DS1086LPMB1 peripheral module
_________________________________________________________________ maxim integrated products 6 figure 5. DS1086LPMB11 peripheral module pcb layoutinner layer 2 (power) figure 6. DS1086LPMB11 peripheral module pcb layoutsolder side figure 7. DS1086LPMB11 peripheral module component placement guidesolder side DS1086LPMB1 peripheral module
part type DS1086LPMB1# module _________________________________________________________________ maxim integrated products 7 ordering information # denotes rohs compliant. DS1086LPMB1 peripheral module
revision number revision date description pages changed 0 5/12 initial release maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 8 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history DS1086LPMB1 peripheral module
|
